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integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 1 advance information rev. 00b 11/11/02 is61lscs25672 is61lscs51236 issi ? copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtai n the latest version of this device specification before relying on any published information and before placing orders for products. bottom view 209-ball, 14 mm x 22 mm bga 1 mm ball pitch, 11 x 19 ball array sigmaram family overview the is61lscs series rams are built in compliance with the sigmaram pinout standard for synchronous srams. the implementations are 18,874,368-bit (18mb) srams. these are the first in a family of wide, very low voltage cmos i/o srams designed to operate at the speeds needed to implement economical high performance networking systems. issi ? s rams are offered in a number of configurations that emulate other synchronous srams, such as burst rams, nbt rams, late write, or double data rate (ddr) srams. the logical differences between the protocols employed by these rams hinge mainly on various combinations of address bursting, output data registering and write cueing. rams allow a user to implement the interface protocol best suited to the task at hand. this specific product is common i/o, sdr, pipelined, and in the family is identified as 1x1lp. advance information november 2002 ram 256k x 72, 512k x 36 18mb synchronous sram features ? jedec sigmaram pinout and package standard single 1.8v power supply (v dd ): 1.7v (min) to 1.9v (max) dedicated output supply voltage (v ddq ): 1.8v or 1.5v typical lvcmos-compatible i/o interface common data i/o pins (dqs) single data rate (sdr) data transfers late write pipelined (pl) read operations burst and non-burst read and write operations, selectable via dedicated control pin (adv) internally controlled linear burst address sequencing during burst operations burst length of 2, 3, or 4, with automatic address wrap full read/write coherency byte write capability two cycle deselect single-ended input clock (clk) data-referenced output clocks (cq/, cq ) selectable output driver impedance via dedicated control pin (zq) echo clock outputs track data output drivers depth expansion capability (2 or 4 banks) via programmable chip enables (e2, e3, ep2, ep3) jtag boundary scan (subset of ieee standard 1149.1) 209 ball (11x19), 1mm pitch, 14mm x 22mm ball grid array (bga) package
2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advance information rev. 00b 11/11/02 is61lscs25672 is61lscs51236 issi ? functional description because sigmaram is a synchronous device, address, data inputs, and read/write control inputs are captured on the rising edge of the input clock. write cycles are internally self-timed and initiated by the rising edge of the clock input. this feature eliminates complex off-chip write pulse generation required by asynchronous srams and simplifies input signal timing. is61lscs25672 pinout 256k x 72 common i/o?top view 1234567891011 a dqg dqg a e2 a adv a e3 a dqb dqb (16m) (8m) b dqg dqg bc bg nc w a bb bf dqb dqb c dqg dqg bh bd nc e1 nc be ba dqb dqb (128m) d dqg dqg gnd nc nc mcl nc nc gnd dqb dqb e dqpg dqpc v ddq v ddq v dd v dd v dd v ddq v ddq dqpf dqpb f dqc dqc gnd gnd gnd zq gnd gnd gnd dqf dqf g dqc dqc v ddq v ddq v dd ep2 v dd v ddq v ddq dqf dqf h dqc dqc gnd gnd gnd ep3 gnd gnd gnd dqf dqf j dqc dqc v ddq v ddq v dd m4 v dd v ddq v ddq dqf dqf k cq2 cq2 clk nc gnd mcl gnd nc nc cq1 cq1 l dqh dqh v ddq v ddq v dd m2 v dd v ddq v ddq dqa dqa m dqh dqh gnd gnd gnd m3 gnd gnd gnd dqa dqa n dqh dqh v ddq v ddq v dd mch v dd v ddq v ddq dqa dqa p dqh dqh gnd gnd gnd mcl gnd gnd gnd dqa dqa r dqpd dqph v ddq v ddq v dd v dd v dd v ddq v ddq dqpa dqpe t dqd dqd gnd nc nc mcl nc nc gnd dqe dqe u dqd dqd nc a nc a nc a nc dqe dqe (64m) (32m) v dqd dqd a a a a1 a a a dqe dqe w dqd dqd tms tdi a a0 a tdo tck dqe dqe 11 x 19 ball bga?14 x 22 mm 2 body?1 mm ball pitch single data rate rams incorporate a rising-edge-triggered output register. for read cycles, ram?s output data is temporarily stored by the edge-triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. is61lscs series rams are implemented with issi?s high performance cmos technology and are packaged in a 209-ball bga.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 3 advance information rev. 00b 11/11/02 is61lscs25672 is61lscs51236 issi ? is61lscs51236 pinout 512k x 36 common i/o?top view 1234567891011 a nc nc a e2 a adv a e3 a dqb dqb (16m) bnc nc bc nc a w a bb nc dqb dqb (x36) cnc nc nc bd nc e1 nc nc ba dqb dqb (128m) d nc nc gnd nc nc mcl nc nc gnd dqb dqb e nc dqpc v ddq v ddq v dd v dd v dd v ddq v ddq nc dqpb f dqc dqc gnd gnd gnd zq gnd gnd gnd nc nc g dqc dqc v ddq v ddq v dd ep2 v dd v ddq v ddq nc nc h dqc dqc gnd gnd gnd ep3 gnd gnd gnd nc nc j dqc dqc v ddq v ddq v dd m4 v dd v ddq v ddq nc nc k cq2 cq2 clk nc gnd mcl gnd nc nc cq1 cq1 lnc nc v ddq v ddq v dd m2 v dd v ddq v ddq dqa dqa m nc nc gnd gnd gnd m3 gnd gnd gnd dqa dqa nnc nc v ddq v ddq v dd mch v dd v ddq v ddq dqa dqa p nc nc gnd gnd gnd mcl gnd gnd gnd dqa dqa r dqpd nc v ddq v ddq v dd v dd v dd v ddq v ddq dqpa nc t dqd dqd gnd nc nc mcl nc nc gnd nc nc u dqd dqd nc a nc a nc a nc nc nc (64m) (32m) v dqd dqd a a a a1 a a a nc nc w dqd dqd tms tdi a a0 a tdo tck nc nc 11 x 19 ball bga?14 x 22 mm 2 body?1 mm ball pitch
4 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advance information rev. 00b 11/11/02 is61lscs25672 is61lscs51236 issi ? pin description table symbol pin location description type comments a a3, a5, a7, a9, b7, u4, address input ? u6, u8, v3, v4, v5, v6, v7, v8, v9, w5, w6, w7 a b5 address input x36 version adv a6 advance input active high bx b3, c9 byte write enable input active low (all versions) bx b8, c4 byte write enable input active low (x36 and x72 versions) bx b4, b9, c3, c8 byte write enable input active low (x72 version only) ck k3 clock input active high cq k1, k11 echo clock output active high cq k2, k10 echo clock output active low dq e2, f1, f2, g1, g2, h1, data i/o input/output x36, and x72 versions h2, j1, j2, l10, l11, m10, m11, n10, n11, p10, p11, r10 a10, a11, b10, b11, data i/o input/output c10, c11, d10, d11, e11, r1, t1, t2, u1, u2, v1, v2, w1, w2 dq a1, a2, b1, b2, c1, c2, data i/o input/output x72 version only d1, d2, e1, e10, f10, f11, g10, g11, h10, h11, j10, j11, l1, l2, m1, m2, n1, n2, p1, p2, r2, r11, t10, t11, u10, u11, v10, v11, w10, w11 e1 c6 chip enable input active low e2 & e3 a4, a8 chip enable input programmable active high or low ep2 & ep3 g6, h6 chip enable program pin input ? tck w9 test clock input active high tdi w4 test data in input ? tdo w8 test data out output ? tms w3 test mode select input ? m2, m3 & m4 l6, m6, j6 mode control pins input m ust tie to high, high, low mcl d6, k6, p6, t6 must connect low input ? mch n6 must connect high input ?
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 5 advance information rev. 00b 11/11/02 is61lscs25672 is61lscs51236 issi ? pin description table symbol pin location description type comments c5, d4, d5, d7, d8, k4, nc k8, k9, t4, t5, t7, no connect ? not connected to die (all versions) t8, u3, u5, u7, u9 nc b5 no connect ? not connected to die (x72 version) nc c7 no connect ? not connected to die (x72/x36 versions) a1, a2, b1, b2, b4, b9, c1, c2, c3, c8, d1, d2, e1, e10, f10, f11, g10, nc g11, h10, h11, j10, j11, no connect ? not connected to die (x36 version) l1, l2, m1, m2, n1, n2, p1, p2, r2, r11, t10, t11, u10, u11, v10, v11, w10, w11 w b6 write input active low e5, e6, e7, g5, g7, v dd j5, j7, l5, l7, n5, core power supply input 1.8 v nominal n7, r5, r6, r7 e3, e4, e8, e9, j3, j4, v ddq j8, j9, l3, l4, l8, output driver power supply input 1.8 v or 1.5 v nominal l9, n3, n4, n8, n9, r3, r4, r8, r9 g3, g4, g8, g9 d3, d9, f3, f4, f5, f7, f8, f9, h3, h4, h5, h7, gnd h8, h9, k5, k7, m3, m4, ground input ? m5, m7, m8, m9, p3, p4, p5, p7, p8, p9, t3, t9 zq f6 output impedance control input low = low impedance [high drive] high = high impedance [low drive] default = high
6 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advance information rev. 00b 11/11/02 is61lscs25672 is61lscs51236 issi ? background the central characteristics of the issi rams are that they are extremely fast and consume very little power. because both operating and interface power is low, rams can be implemented in a wide (x72) configuration, providing very high single package bandwidth (in excess of 20 gb/s in ordinary pipelined configuration) and very low random access latency (~3 ns). the use of very low voltage circuits in the core and 1.8v or 1.5v interface voltages allow the speed, power and density performance of rams. although the sigma ram family pinouts have been de- signed to support a number of different common read and write protocol options, not all sigmaram implementa- tions will support all possible protocols. the following timing diagrams provide a quick comparison between read and write protocols options available in the context of the sigmaram standard. this data sheet covers the single data rate (non-ddr) , pipelined read sigmaram. the character of the applications for fast synchronous srams in networking systems are extremely diverse. rams have been developed to address the diverse needs of the networking market in a manner that can be supported with a unified development and manufacturing infrastructure. rams address each of the bus protocol options commonly found in networking systems. this allows the ram to find application in radical shrinks and speed-ups of existing networking chip sets that were designed for use with older srams, like the nbt or nt, late write, or double data rate srams, as well as with new chip sets and asic?s that employ the echo clocks and realize the full potential of the rams. late write?pipelined read ( 1x1lp). for reference only. a b c d e f r w r w r w qa db qc dd qe ck address control dq cq double late write?pipelined read ( 1x1dp). for reference only. a b c d e f r x w r x w qa dc qd df ck address control dq cq common i/o sigmaram family mode comparison?late write vs. double late write
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 7 advance information rev. 00b 11/11/02 is61lscs25672 is61lscs51236 issi ? read operations pipelined read read operation is initiated when the following conditions are satisfied at the rising edge of clock: all three chip enables ( e1 , e2, and e3) are active, the write enable input signal ( w ) is deasserted high, and adv is asserted low. the address presented to the address inputs is latched into the address register and presented to the memory core and control logic. the control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. at the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins. write operations write operation occurs when the following conditions are satisfied at the rising edge of clock: all three chip enables ( e1 , e2, and e3) are active and the write enable input signal ( w ) is asserted low. data is taken at the next rising edge of clock, as a late write operation. a b c d e f r x w r x w ck address control dq cq dc0 qa0 qa1 qd0 qd1 df0 dc1 double data rate write?double data rate read ( 1x2lp). for reference only.
8 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advance information rev. 00b 11/11/02 is61lscs25672 is61lscs51236 issi ? single data rate pipelined read late write with pipelined read clk axx c d e f address e1 w cq dq read deselect read read read qa qc qd read clk a cd address e1 w cq dq read deselect write db b read deselect write qa qd xx xx deselect dc xx
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 9 advance information rev. 00b 11/11/02 is61lscs25672 is61lscs51236 issi ? special functions burst cycles rams provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementations. the adv control pin, when driven high, commands the ram to advance the internal ad- dress counter and use the counter generated address to read or write the ram. the starting address for the first cycle in a burst cycle series is loaded into the ram by driving the adv pin low, into load mode. burst order the burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been accessed. sigmarams always count in linear burst order. linear burst order a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 note: 1. the burst counter wraps to initial state on the 5th rising edge of clock. sigma pipelined burst reads with counter wrap-around clk a2 address e1 w cq dq read a2 a1 a3 a0 internal address a3 a2 xx xx xx xx xx adv continue bursting 10 11 00 01 qa2 qa3 qa0 qa1 counter wraps continue bursting continue bursting continue bursting continue bursting
10 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advance information rev. 00b 11/11/02 is61lscs25672 is61lscs51236 issi ? echo clock control in two banks of sigma pipelined srams echo clock rams feature echo clocks, cq1, cq2, cq1 , and cq2 that track the performance of the output drivers. the echo clocks are delayed copies of the main ram clock, clk. echo clocks are designed to track changes in output driver delays due to variance in die temperature and supply voltage. the echo clocks are designed to fire with the rest of the data output drivers. sigma rams provide both in-phase, or true, echo clock outputs (cq1 and cq2) and inverted echo clock outputs ( cq1 and cq2 ). it should be noted that deselection of the ram via e2 and e3 also deselects the echo clock output drivers. the deselection of echo clock drivers is always pipelined to the same degree as output data. deselection of the ram via e1 does not deactivate the echo clocks. in some applications it may be appropriate to pause between banks; to deselect both rams with e1 before resuming read operations. an e1 deselect at a bank switch will allow at least one clock to be issued from the new bank before the first read cycle in the bank. although the following drawing illustrates a e1 read pause upon switching from bank 1 to bank 2, a write to bank 2 would have the same effect, causing the ram in bank 2 to issue at least one clock before it is needed. a b c d e f qa qc qb qd read read read read read read clk address e1 e2 bank 1 e2 bank 2 dq bank 1 dq bank 2 cq bank 1 cq bank 2 cq1+ cq2 note: e1 does not deselect the echo clock outputs. echo clock outputs are synchronously deselected by e2 or e3 being sampled false.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 11 advance information rev. 00b 11/11/02 is61lscs25672 is61lscs51236 issi ? pipelined read bank switch with e1 deselect a xx c d e f qa qc qd read no op read read read read clk address e1 e2 bank 1 e2 bank 2 dq bank 1 dq bank 2 cq bank 1 cq bank 2 cq1+ cq2 note: e1 does not deselect the echo clock outputs. echo clock outputs are synchronously deselected by e2 or e3 being sampled false. output driver impedance control sigmarams may be supplied with either selectable (high) impedance output drivers. the zq pin of sigmarams supplied with selectable impedance drivers, allows selection between ram nominal drive strength (zq low) for multi-drop bus applications and low drive strength (zq floating or high) point-to-point applications. the impedance of the data and clock output drivers in these devices can be controlled via the static input zq. when zq is tied "low", output driver impedance is set to ~25 ? . when zq is tied "high" or left unconnected, output driver impedance is set to ~50 ?. see the dc electrical characteristics section for further information. the sram requires 32k cycles of power-up time after v dd reaches its operating range. output driver characteristics - tbd
12 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advance information rev. 00b 11/11/02 is61lscs25672 is61lscs51236 issi ? programmable enables srams feature two user-programmable chip enable inputs, e2 and e3. the sense of the inputs, whether they function as active low or active high inputs, is determined by the state of the programming inputs, ep2 and ep3. for example, if ep2 is held at v dd , e2 functions as an active high enable. if ep2 is held to gnd , e2 functions as an active low chip enable input. bank enable truth table ep2 ep3 e2 e3 bank 0 gnd gnd active low active low bank 1 gnd v dd active low active high bank 2 v dd gnd active high active low bank 3 v dd v dd active high active high example four bank depth expansion schematic programmability of e2 and e3 allows four banks of depth expansion to be accomplished with no additional logic. by programming the enable inputs of four srams in binary sequence (00, 01, 10, 11) and driving the enable inputs with two address inputs, four srams can be made to look like one larger ram to the system. a e3 e2 e1 clk w dq cq a e3 e2 e1 clk w dq cq a 0 -a n-2 a n-1 a n a e3 e2 e1 clk w dq cq a e3 e2 e1 clk w dq cq a 0 -a n-2 a n-1 a n a e3 e2 e1 clk w dq cq a e3 e2 e1 clk w dq cq a 0 -a n-2 a n-1 a n a e3 e2 e1 clk w dq cq a e3 e2 e1 clk w dq cq a 0 -a n-2 a n-1 a n bank 0 bank 1 bank 2 bank 3 a0-an e1 clk w dq0-dqn cq
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 13 advance information rev. 00b 11/11/02 is61lscs25672 is61lscs51236 issi ? synchronous truth table clk e1 e1 e1 e1 e1 e adv w w w w w bw bw bw bw bw previous current operation dq/cq dq/cq (tn) (tn) (tn) (tn) (tn) operation (tn) (tn+1) 0 1 x f 0 x x x bank deselect *** hi-z 0 1 x x 1 x x bank deselect bank deselect (continue) hi-z hi-z 0 1 1 t 0 x x x deselect *** hi-z/cq 0 1 x x 1 x x deselect deselect (continue) h i-z/cq hi-z/cq 0 1 0 t 0 0 t x write *** dn/cq loads new address (tn) stores dqx if bwx = 0 0 1 0 t 0 0 f x write (abort) *** h i-z/cq loads new address no data stored 0 1 x x 1 x t write write continue dn-1/cq dn/cq increments address by 1 (tn-1) (tn) stores dqx if bwx = 0 0 1 x x 1 x f write write continue (abort) dn-1/cq hi-z/cq increments address by 1 (tn-1) no data stored 0 1 0 t 0 1 x x read *** qn/cq loads new address (tn) 0 1 x x 1 x x read read continue qn-1/cq qn/cq increments address by 1 (tn-1) (tn) notes: 1. if e2 = ep2 and e3 = ep3 then e = ?t? else e = ?f?. 2. if one or more bwx = 0 then bw = ?t? else bw = ?f?. 3. ?1? = input ?high?; ?0? = input ?low?; ?x? = input ?don?t care?; ?t? = input ?true?; ?f? = input ?false?. 4. ?***? indicates that the dq input requirement/output state and cq output state are determined by the previous operation. 5. dqs are tri-stated in response to bank deselect, deselect, and write commands, one full cycle after the command is sampled. 6. cqs are tri-stated in response to bank deselect commands only, one full cycle after the command is sampled. 7. up to 3 continue operations may be initiated after initiating a read or write operation to burst transfer up to 4 distinct pi eces of data per single external address input. if a fourth (4th) continue operation is initiated, the internal address wraps back to the initial exter nal (base) address.
14 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advance information rev. 00b 11/11/02 is61lscs25672 is61lscs51236 issi ? read/write control state diagram read read continue write write continue deselect bank deselect x,f,0,x or x,x,1,x 1,t,0,x or x,x,1,x 0,t,0,1 x,x,1,x x,x,1,x x,f,0,x 0,t,0,0 x,f,0,x x,f,0,x x,f,0,x 0,t,0,0 0,t,0,0 0,t,0,0 0,t,0,0 0,t,0,1 0,t,0,0 0,t,0,1 0,t,0,1 0,t,0,1 1,t,0,x 1,t,0,x 1,t,0,x 1,t,0,x 1,t,0,x x,x,1,x x,x,1,x 0,t,0,1 x,f,0,x notes: 1. the notation ?x,x,x,x? controlling the state transitions above indicate the states of inputs e1 , e, adv, and w respectively. 2. if (e2 = ep2 and e3 = ep3) then e = ?t? else e = ?f?. 3. ?1? = input ?high?; ?0? = input ?low?; ?x? = input ?don?t care?; ?t? = input ?true?; ?f? = input ?false?.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 15 advance information rev. 00b 11/11/02 is61lscs25672 is61lscs51236 issi ? absolute maximum ratings (all voltages reference to gnd ) symbol description value unit v dd voltage on v dd pins ?0.5 to 2.5 v v ddq voltage in v ddq pins ?0.5 to 2.3 v v i/o voltage on i/o pins ?0.5 to v ddq +0.5 ( 2.3 v max.) v v in voltage on other input pins ?0.5 to v ddq +0.5 ( 2.3 v max.) v i in input current on any pin 100 ma dc i out output current on any pin 100 ma dc t j maximum junction temperature 125 c t stg storage temperature -55 to 125 c note: permanent device damage may occur if absolute maximum ratings are exceeded. operation should be limited to recommended operating conditions. exposure to conditions exceeding recommended operating conditions, for an extended period of time, may affect reliability of this component. current state & next state definition for read/write control state diagram ? ? ? ? n n+1 n+2 n+3 current state next state ck command ? transition current state (n) input command code next state (n+1) key power supply characteristics (t a = 0 min., 25 typ, 70 max c) symbol parameter min. typ. max. unit v dd supply voltage 1.7 1.8 1.9 v v ddq (1) 1.8 v i/o supply voltage 1.7 1.8 v dd v 1.5 v i/o supply voltage 1.4 1.5 1.6 v note: 1. unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 1.4 v v ddq 1.6v (i.e., 1.5 v i/o) and 1.7 v v ddq 1.95 v (i.e., 1.8 v i/o) and quoted at whichever condition is worst case.
16 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advance information rev. 00b 11/11/02 is61lscs25672 is61lscs51236 issi ? cmos i/o dc input characteristics symbol parameter v ddq min. typ. max. unit v ih cmos input high voltage 1.8 1.2 ? v ddq + 0.3 v 1.5 1.0 ? v ddq + 0.3 v il cmos input low voltage 1.8 ?0.3 ? 0.6 v 1.5 ?0.3 ? 0.5 note: for devices supplied with cmos input buffers. compatible with both 1.8 v and 1.5 v i/o drivers. i/o capacitance (t a = 25 c, f = 1 mh z ) symbol parameter test conditions min. max. unit c a address input capacitance v in = 0 v ? 3.5 pf c b control input capacitance v in = 0 v ? 3.5 pf c ck clock input capacitance v in = 0 v ? 3.5 pf c dq data output capacitance v out = 0 v ? 4.5 pf c cq cq clock output capacitance v out = 0 v ? 4.5 pf note: these parameters are sampled and not 100% tested. undershoot measurement and timing overshoot measurement and timing 20% t kc 50% gnd v ih gnd - 1.0v 20% t kc 50% v dd + 1.0v v dd v il
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 17 advance information rev. 00b 11/11/02 is61lscs25672 is61lscs51236 issi ? ac test conditions (v dd = 1.8v 0.1v, t a = 0 to 85c) parameter symbol conditions units v ddq 1.5v 0.1 1.8 0.1 v input high level v ih 1.25 1.4 v input low level v il 0.25 0.4 v input rise & fall time 2.0 2.0 v/ns input reference level 0.75 0.9 v clock input high voltage v kih 1.25 1.4 v clock input low voltage v kil 0.25 0.4 v clock input rise & fall time 2.0 2.0 v/ns clock input reference level 0.75 0.9 v output reference level 0.75 0.9 v output load conditions zq = v ih see below see below notes: 1. include scope and jig capacitance. 2. test conditions as specified with output loading as shown unless otherwise noted. ac test loads dq 0.75v 50 ? 50 ? 16.7 ? 16.7 ? 50 ? 16.7 ? 0.75v 50 ? 5 pf 5 pf v ddq = 1.5v dq 0.9v 50 ? 50 ? 16.7 ? 16.7 ? 50 ? 16.7 ? 0.9v 50 ? 5 pf 5 pf v ddq = 1.8v figure 1 (v ddq = 1.5v) figure 2 (v ddq = 1.8v)
18 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advance information rev. 00b 11/11/02 is61lscs25672 is61lscs51236 issi ? selectable impedance output driver dc electrical characteristics symbol parameter test conditions min. max. units v ohl (1) low drive output high voltage i ohl = ?4 ma v ddq ? 0.4 ? v v oll (1) low drive output low voltage i oll = 4 ma ? 0.4 v v ohh (2) high drive output high voltage i ohh = ?8 ma v ddq ? 0.4 ? v v olh (2) high drive output low voltage i olh = 8 ma ? 0.4 v notes: 1. zq = 1; high impedance output driver setting 2. zq = 0; low impedance output driver setting output resistance symbol parameter test conditions min. typ. max. units r out output resistance v oh , v ol = v ddq /2 17 25 33 ? zq = v il v oh , v ol = v ddq /2 35 50 65 ? zq = v ih
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 19 advance information rev. 00b 11/11/02 is61lscs25672 is61lscs51236 issi ? dc electrical characteristics (v dd = 1.8v 0.1v, gnd = 0v, t a = 0 to 85 c) symbol parameter test conditions min typ max units i li input leakage current v in = gnd to v ddq -5 ? 5 ua (address, control, clock) i mli input leakage current v min = gnd to v dd -10 ? 10 ua (ep2, ep3, m2, m3, m4, zq) i dli input leakage current v din = gnd to v ddq -10 ? 10 ua (data) operating currents symbol p arameter test conditions -333 -300 -250 units com. ind. com. ind. com. ind. i cc operating current e1 < v il max. pipeline x72 650 ma t khkh > t khkh min. x36 550 all other inputs v il > v in > v ih i sb 1 bank deselect current e1 < v ih min. or pipeline x72 250 ma & & e2 or e3 false x36 225 i sb 2 chip disable current t khkh > t khkh min. all other inputs v il > v in > v ih i sb 3 cmos deselect current device deselected pipeline x72 150 ma all inputs x36 150 gnd+0.10v > v in > v dd ?0.10v note: com. = 0c to 70c ind. = ?40c to +85c
20 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advance information rev. 00b 11/11/02 is61lscs25672 is61lscs51236 issi ? ac electrical characteristics -333 -300 -250 symbol parameter min max min max min max unit t khkh clock cycle time 3.0 ? 3.3 ? 4.0 ? ns t khkl clock high time 1.2 ? 1.3 ? 1.5 ? ns t klkh clock low time 1.2 ? 1.3 ? 1.5 ? ns t khcx 1 (2) clock high to echo clock low-z 0.5 ? 0.5 ? 0.5 ? ns t khch clock high to echo clock high 0.5 1.5 0.5 1.7 0.5 2.0 ns t chcl (2) echo clock high time t khkl 200 ps t khkl 200 ps t khkl 250 ps ns t klcl clock low to echo clock low 0.5 1.5 0.5 1.7 0.5 2.0 ns t clch (2) echo clock low time t klkh 200 ps t klkh 200 ps t klkh 250 ps ns t khcz (1, 2) clock high to echo clock high-z ? 1.5 ? 1.7 ? 2.0 ns t khqx 1 (1) clock high to output in low-z 0.5 ? 0.5 ? 0.5 ? ns t khqv clock high to output valid ? 1.6 ? 1.8 ? 2.1 ns t khqx clock high to output invalid 0.5 ? 0.5 ? 0.5 ? ns t khqz (1) clock high to output in high-z 0.5 1.6 0.5 1.8 0.5 2.1 ns t chqv (2) echo clock high to output valid ? 0.4 ? 0.4 ? 0.5 ns t chqx (2) output invalid to echo clock high ? ?0.4 ? ?0.4 ? ?0.5 ns t avkh address valid to clock high 0.6 ? 0.7 ? 0.8 ? ns t khax clock high to address don?t care 0.4 ? 0.4 ? 0.5 ? ns t evkh enable valid to clock high 0.6 ? 0.7 ? 0.8 ? ns t khex clock high to enable don?t care 0.4 ? 0.4 ? 0.5 ? ns t wvkh write valid to clock high 0.6 ? 0.7 ? 0.8 ? ns t khwx clock high to write don?t care 0.4 ? 0.4 ? 0.5 ? ns t bvkh byte write valid to clock high 0.6 ? 0.7 ? 0.8 ? ns t khbx clock high to byte write don?t care 0.4 ? 0.4 ? 0.5 ? ns t dvkh data in valid to clock high 0.6 ? 0.7 ? 0.8 ? ns t khdx clock high to data in don?t care 0.4 ? 0.4 ? 0.5 ? ns t advvkh adv valid to clock high 0.6 ? 0.7 ? 0.8 ? ns t khadvx clock high to adv don?t care 0.4 ? 0.4 ? 0.5 ? ns notes: 1. measured at 100 mv from steady state. not 100% tested. 2. guaranteed by design. not 100% tested. 3. for any specific temperature and voltage t khcz < t khcx 1.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 21 advance information rev. 00b 11/11/02 is61lscs25672 is61lscs51236 issi ? ac electrical characteristics -225 -200 symbol parameter min max min max unit t khkh clock cycle time 4.5 ? 5.0 ? ns t khkl clock high time 1.8 ? 2.0 ? ns t klkh clock low time 1.8 ? 2.0 ? ns t khcx 1 (2) clock high to echo clock low-z 0.5 ? 0.5 ? ns t khch clock high to echo clock high 0.5 2.5 0.5 3.0 ns t chcl (2) echo clock high time t khkl 250 ps t khkl 250 ps ns t klcl clock low to echo clock low 0.5 2.5 0.5 3.0 ns t clch (2) echo clock low time t klkh 200 ps t klkh 200 ps ns t khcz (1, 2) clock high to echo clock high-z ? 2.5 ? 3.0 ns t khqx 1 (1) clock high to output in low-z 0.5 ? 0.5 ? ns t khqv clock high to output valid ? 2.6 ? 3.1 ns t khqx clock high to output invalid 0.5 ? 0.5 ? ns t khqz (1) clock high to output in high-z 0.5 2.6 0.5 3.1 ns t chqv (2) echo clock high to output valid ? 0.5 ? 0.5 ns t chqx (2) output invalid to echo clock high ? ?0.5 ? ?0.5 ns t avkh address valid to clock high 1.1 ? 1.5 ? ns t khax clock high to address don?t care 0.5 ? 0.5 ? ns t evkh enable valid to clock high 1.1 ? 1.5 ? ns t khex clock high to enable don?t care 0.5 ? 0.5 ? ns t wvkh write valid to clock high 1.1 ? 1.5 ? ns t khwx clock high to write don?t care 0.5 ? 0.5 ? ns t bvkh byte write valid to clock high 1.1 ? 1.5 ? ns t khbx clock high to byte write don?t care 0.5 ? 0.5 ? ns t dvkh data in valid to clock high 1.1 ? 1.5 ? ns t khdx clock high to data in don?t care 0.5 ? 0.5 ? ns t advvkh adv valid to clock high 1.1 ? 1.5 ? ns t khadvx clock high to adv don?t care 0.5 ? 0.5 ? ns notes: 1. measured at 100 mv from steady state. not 100% tested. 2. guaranteed by design. not 100% tested. 3. for any specific temperature and voltage t khcz < t khcx 1.
22 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advance information rev. 00b 11/11/02 is61lscs25672 is61lscs51236 issi ? timing parameter key?pipelined read cycle timing timing parameter key?late write mode control and data in timing note: tn vkh = t evkh , t wvkh , t bvkh , etc. and t kh n x = t khex , t khwx , t khbx , etc. qb t klkh t khkh t khkl t khqz t khqx t khqv t khqx1 t cqhqv t khcqh t khcqx1 t cqhcql t cqlcqh t cqhqx t khcqz = cq high z t khax t avkh c d e ck dq cq b a b c ck address e1,e2,e3 w, bn, adv t avkh t khax t n vkh t kh n x dq da t dvkh t khdx control "a"
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 23 advance information rev. 00b 11/11/02 is61lscs25672 is61lscs51236 issi ? jtag port operation overview these devices provide a jtag test access port (tap) and boundary scan interface using a limited set of ieee std. 1149.1 functions. this test mode is intended to provide a mechanism for testing the interconnect between master (processor, controller, etc.), srams, other components, and the printed circuit board. in conformance with a subset of ieee std. 1149.1, these devices contain a tap controller and four tap registers. the tap registers consist of one instruction register jtag pin descriptions pin pin name i/o description tck test clock in clocks all tap events. all inputs are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms test mode select in the tms input is sampled on the rising edge of tck. this is the command input for the tap controller. an undriven tms input will produce the same result as a logic one input level. tdi test data in in the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed between tdi and tdo. the register placed between tdi and tdo is determined by the state of the tap controller and the instruction that is currently loaded in the tap instruction register (refer to the tap controller state diagram). an undriven tdi pin will produce the same result as a logic one input level. tdo test data out out output that is active depending on the state of the tap controller. output changes in response to the falling edge of tck. this is the output side of the serial registers placed between tdi and tdo. note: this device does not have a trst (tap reset) pin. trst is optional in ieee 1149.1. the test-logic-reset state is entered while tms is held high for five rising edges of tck. the tap controller is also reset automatically at power-up. and three data registers (id, bypass, and boundary scan registers). disabling the jtag port it is possible to use this device without utilizing the jtag port. the port is reset at power-up and will remain inactive unless clocked. to assure normal operation of the ram with the jtag port unused, tck should be tied low, tdi and tms may be left floating or tied to v dd . tdo should be left unconnected.
24 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advance information rev. 00b 11/11/02 is61lscs25672 is61lscs51236 issi ? jtag tap block diagram bypass register instruction register id code register boundary scan register . . . . . . . . 0 2 1 0 31 30 29 2 1 0 n 2 1 0 test access port (tap) controller tdi tms tck tdo jtag port registers overview the jtag registers, referred to as test access port (tap) registers, are selected (one at a time) via the sequences of 1s and 0s applied to tms as tck is strobed. each of the tap registers are serial shift registers that capture serial input data on the rising edge of tck and push serial data out on the next falling edge of tck. when a register is selected, it is placed between the tdi and tdo pins. instruction register the instruction register holds the instructions that are executed by the tap controller when it is moved into the run, test/idle, or the various data register states. in- structions are 3 bits long. the instruction register can be loaded when it is placed between the tdi and tdo pins. the instruction register is automatically preloaded with the idcode instruction at power-up or whenever the controller is placed in test-logic-reset state. bypass register the bypass register is a single-bit register that can be placed between tdi and tdo. it allows serial test data to be passed through the ram?s jtag port to another device in the scan chain with as little delay as possible. boundary scan register the boundary scan register is a collection of flip flops that can be preset by the logic level found on the ram?s input or i/o pins. the flip flops are then daisy chained together so the levels found can be shifted serially out of the jtag port?s tdo pin. the boundary scan register also includes a number of place holder flip flops (always set to a logic 1). the relationship between the device pins and the bits in the boundary scan register is described in the following scan order table. the boundary scan register, under the control of the tap controller, is loaded with the contents of the rams i/o ring when the controller is in capture-dr state and then is placed between the tdi and tdo pins when the controller is moved to shift-dr state. sample-z, sample/preload and extest instructions can be used to activate the boundary scan register.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 25 advance information rev. 00b 11/11/02 is61lscs25672 is61lscs51236 issi ? jtag tap controller state diagram select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test idle 11 1 11 11 1 1 1 1 1 1 1 0 0 0 0 1 00 0 0 0 0 0 0 0 0 0 10 identification (id) register the id register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in capture-dr state with the idcode command loaded in the instruction register. the code is loaded from a 32-bit on-chip rom. it describes various attributes of the ram as indicated below. the register is then placed between the tdi and tdo pins when the controller is moved into shift-dr state. bit 0 in the register is the lsb and the first to reach tdo when shifting begins. bit # 31302928 2726 2524 2322 212019 1817 161514 1312 1110 9 8 7 6 5 4 3 2 1 0 x72 xxxx00 00 00 000 00 011 00 0001 1 010 10 1 1 x36 xxxx00000000000010 0000011010101 1 presence register die i/o issi technology revision not used configuration jedec vendor code id code id register contents
26 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advance information rev. 00b 11/11/02 is61lscs25672 is61lscs51236 issi ? jtag tap instruction set summary instruction code description extest (1) 000 places the boundary scan register between tdi and tdo. when extest is selected, data will be driven out of the dq pad. idcode (1,2) 001 preloads id register and places it between tdi and tdo. sample-z (1) 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all data and clock output drivers to high-z. rfu (1) 011 do not use this instruction; reserved for future use. replicates bypass instruction. places bypass register between tdi and tdo. sample/preload (1) 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. private (1) 101 private instruction. rfu (1) 110 do not use this instruction; reserved for future use. bypass (1) 111 places bypass register between tdi and tdo. notes: 1. instruction codes expressed in binary, msb on left, lsb on right. 2. default instruction automatically loaded at power-up and in test-logic-reset state. tap controller instruction set overview there are two classes of instructions defined in the standard 1149.1-1990 ; standard ( public ) instructions, and device specific (private) instructions. some public instructions are mandatory for 1149.1 compliance. optional public instructions must be implemented in prescribed ways. the tap on this device may be used to monitor all input and i/o pads. this device will not perform intest but can preform the preload portion of the sample/preload command. when the tap controller is placed in capture-ir state, the two least significant bits of the instruction register are loaded with 01. when the controller is moved to the shift-ir state, the instruction register is placed between tdi and tdo. in this state the desired instruction is serially loaded through the tdi input (while the previous contents are shifted out at tdo). for all instructions, the tap executes newly loaded instructions only when the controller is moved to update-ir state. the tap instruction set for this device is listed in the jtag tap instruction set summary.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 27 advance information rev. 00b 11/11/02 is61lscs25672 is61lscs51236 issi ? jtag dc recommended operating conditions (t a = 0 to 85c) symbol parameter test conditions min. max. unit v tih jtag input high voltage 1.2 v dd +0.3 v v til jtag input low voltage -0.3 0.6 v v toh jtag output high voltage cmos i toh = -100 ? v dd -0.1 ? v ttl i toh = -8m v dd -0.4 ? v tol jtag output low voltage cmos i tol = 100 ? ? 0.1 v ttl i tol = 8m ? 0.4 i tli jtag input leakage current v tin =gnd to v dd -10 10 ? jtag ac test conditions (v dd = 1.8v 0.1v, t a = 0 to 85c) symbol parameter test conditions unit v tih jtag input high voltage 1.6 v v til jtag input low voltage 0.2 v jtag input rise & fall time 1.0 v/ns jtag input reference level 0.9 v jtag output reference level 0.9 v jtag output load condition see ac test loads
28 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advance information rev. 00b 11/11/02 is61lscs25672 is61lscs51236 issi ? symbol parameter min max unit t thth tck cycle time 20 ? ns t thtl tck high pulse width 8?ns t tlth tck low pulse width 8?ns t mvth tms setup time 5 ? ns t thmx tms hold time 5 ? ns t dvth tdi set up time 5?ns t thdx tdi hold time 5?ns t tlqv tck low to tdo valid ?10ns t tlqx tck low to tdo hold 0?ns jtag port timing diagram tck tms tdi tdo t thtl t tlth t thth t mvth t thmx t dvth t thdx t tlqx t tlqv jtag port ac electrical characteristics
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 29 advance information rev. 00b 11/11/02 is61lscs25672 is61lscs51236 issi ? instruction descriptions bypass when the bypass instruction is loaded to the instruction register, the bypass register is placed between tdi and tdo. this occurs when the tap controller is moved to the shift-dr state. this allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. sample/preload sample/preload is a standard 1149.1 mandatory public instruction. when the sample/preload instruction is loaded in the instruction register , moving the tap controller into the capture-dr state loads the data in the rams input and i/o buffers into the boundary scan register. some boundary scan register locations are not associated with an input or i/o pin, and are loaded with the default state identified in the bsdl file. because the ram clock is independent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring contents while the input buffers are in transition (i.e. in a metastable state). although allowing the tap to sample metastable inputs will not harm the device, repeatable results cannot be expected. ram input signals must be stabilized for long enough to meet the tap?s input data capture set-up plus hold time (t ts plus t th ). the ram?s clock inputs need not be paused for any other tap operation except captur- ing the i/o ring contents into the boundary scan register. moving the controller to shift-dr state then places the boundary scan register between the tdi and tdo pins. extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instruction register is loaded with all logic 0s. the extest command does not block or override the ram?s input pins; therefore, the ram?s internal state is still determined by its input pins. typically, the boundary scan register is loaded with the desired pattern of data with the sample/preload command. then the extest command is used to output the boundary scan register?s contents, in parallel, on the ram?s data output drivers on the falling edge of tck when the controller is in the update-ir state. alternately, the boundary scan register may be loaded in parallel using the extest command. when the extest instruction is selected, the state of all the ram?s input and i/o pins, as well as the default values at scan register locations not associated with a pin (pin marked nc), are transferred in parallel into the boundary scan register on the rising edge of tck in the capture-dr state, the ram?s output pins drive out the value of the boundary scan register location with which each output pin is associated. idcode the idcode instruction causes the id rom to be loaded to the id register when the controller is in capture-dr mode and places the id register between the tdi and tdo pins in shift-dr mode. the idcode instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. sample-z if the sample-z instruction is loaded to the instruction register, all ram outputs are forced to inactive state (high-z) and the boundary scan register is connected between tdi and tdo when the tap controller is moved to the shift-dr state. rfu these instructions are reserved for future use. in this device they replicate the bypass instruction.
30 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advance information rev. 00b 11/11/02 is61lscs25672 is61lscs51236 issi ? boundary scan order assignments (by exit sequence) - ph=place holder x72 ball loc. x36 sequence pkg. ball sequence pkg. ball 1a0w61a0 2av72a 3av83a 4au84a 5av95a 6au66a 7ph (1) u5 7 ph (1) 8aw78a 9ph (1) u7 9 ph (1) 10 mcl t6 10 mcl 11 m3 m6 11 m3 12 m4 j6 12 m4 13 mcl k6 13 mcl 14 mcl d6 14 mcl 15 ph (1) c7 15 ph (1) 16 be c8 17 ba c9 16 ba 18 bb b8 17 bb 19 bf b9 20 w b6 18 w 21 adv a6 19 adv 22 a b7 20 a 23 e3 a8 21 e3 24 a a9 22 a 25 zq f6 23 zq 26 a a3 24 a 27 e2 a4 25 e2 28 a a5 26 a 29 a a7 27 a b5 28 ao36 30 bc b3 29 bc 31 bg b4 32 bh c3 33 bd c4 30 bd 34 ph (1) c5 31 ph (1) 35 e1 c6 32 e1 36 ep2 g6 33 ep2 37 ep3 h6 34 ep3 38 ck k3 35 ck 39 m2 l6 36 m2 note: 1. input of ph register connected to vss.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 31 advance information rev. 00b 11/11/02 is61lscs25672 is61lscs51236 issi ? boundary scan order assignments (by exit sequence) continued: x72 ball loc. x36 sequence pkg. ball sequence pkg. ball 40 mch n6 37 mch 41 mcl p6 38 mcl 42 a v3 39 a 43 a u4 40 a 44 a v4 41 a 45 a v5 42 a 46 a w5 43 a 47 a v6 44 a 48 dqd w2 45 dqd 49 dqd w1 46 dqd 50 dqd v2 47 dqd 51 dqd v1 48 dqd 52 dqd u2 49 dqd 53 dqd u1 50 dqd 54 dqd t2 51 dqd 55 dqd t1 52 dqd 56 dqpd r1 53 dqpd 57 dqph r2 58 dqh p2 59 dqh p1 60 dqh n2 61 dqh n1 62 dqh m2 63 dqh m1 64 dqh l2 65 dqh l1 66 cq2 k2 54 cq2 67 cq2 k1 55 cq2 68 dqc j2 56 dqc 69 dqc j1 57 dqc 70 dqc h2 58 dqc 71 dqc h1 59 dqc 72 dqc g2 60 dqc 73 dqc g1 61 dqc 74 dqc f2 62 dqc 75 dqc f1 63 dqc 76 dqpc e2 64 dqpc 77 dqpg e1 78 dqg d2 79 dqg d1 80 dqg c2 81 dqg c1
32 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 advance information rev. 00b 11/11/02 is61lscs25672 is61lscs51236 issi ? boundary scan order assignments (by exit sequence) continued: x72 ball loc. x36 sequence pkg. ball sequence pkg. ball 82 dqg b2 83 dqg b1 84 dqg a2 85 dqg a1 86 dqb a10 65 dqb 87 dqb a11 66 dqb 88 dqb b10 67 dqb 89 dqb b11 68 dqb 90 dqb c10 69 dqb 91 dqb c11 70 dqb 92 dqb d10 71 dqb 93 dqb d11 72 dqb 94 dqpb e11 73 dqpb 95 dqpf e10 96 dqf f10 97 dqf f11 98 dqf g10 99 dqf g11 100 dqf h10 101 dqf h11 102 dqf j10 103 dqf j11 104 cq1 k11 74 cq1 105 cq1 k10 75 cq1 106 dqa l10 76 dqa 107 dqa l11 77 dqa 108 dqa m10 78 dqa 109 dqa m11 79 dqa 110 dqa n10 80 dqa 111 dqa n11 81 dqa 112 dqa p10 82 dqa 113 dqa8 p11 83 dqa8 114 dqpa9 r10 84 dqpa9 115 dqpe1 r11 116 dqe2 t10 117 dqe3 t11 118 dqe4 u10 119 dqe5 u11 120 dqe6 v10 121 dqe7 v11 122 dqe8 w10 123 dqe9 w11
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 33 advance information rev. 00b 11/11/02 is61lscs25672 is61lscs51236 issi ? ordering information commercial range: 0 c to 70 c frequency order part no. package 256k x 72 250 is61lscs25672-250b 209-ball bga 300 is61lscs25672-300b 209-ball bga 333 is61lscs25672-333b 209-ball bga 512k x 36 250 is61lscs51236-250b 209-ball bga 300 is61lscs51236-300b 209-ball bga 333 IS61LSCS51236-333B 209-ball bga industrial range: -40 c to 85 c frequency speed (ns) order part no. package tbd

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